Atmel /AT91SAM9G10 /UDP /CSR[2]

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Interpret as CSR[2]

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RX_DATA_BK0)RX_DATA_BK0 0 (RXSETUP)RXSETUP 0 (STALLSENTISOERROR)STALLSENTISOERROR 0 (TXPKTRDY)TXPKTRDY 0 (FORCESTALL)FORCESTALL 0 (RX_DATA_BK1)RX_DATA_BK1 0 (DIR)DIR 0EPTYPE 0 (DTGLE)DTGLE 0 (EPEDS)EPEDS 0RXBYTECNT

Description

Endpoint Control and Status Register (ept_num = 0)

Fields

TXCOMP

Generates an IN Packet with Data Previously Written in the DPR

RX_DATA_BK0

Receive Data Bank 0

RXSETUP

Received Setup

STALLSENTISOERROR
TXPKTRDY

Transmit Packet Ready

FORCESTALL

Force Stall (used by Control, Bulk and Isochronous Endpoints)

RX_DATA_BK1

Receive Data Bank 1 (only used by endpoints with ping-pong attributes)

DIR

Transfer Direction (only available for control endpoints)

EPTYPE

Endpoint Type

DTGLE

Data Toggle

EPEDS

Endpoint Enable Disable

RXBYTECNT

Number of Bytes Available in the FIFO

Links

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